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Pin No.
Pin Name
53
XHAC
54
HINT
55
XS16
56
HA1
57
XPDI
58
VDDS
59, 60
HA0, HA2
61
VSS
62, 63
HCS0, HCS1
64
VDD
65
DASP
66 to 69
MDB0 to MDB3
70
VSS
71
MDB4
72
VDD5V
73 to 75
MDB5 to MDB7
76
XMWR
77
VDD
78
XRAS
79, 80
MA0, MA1
81
VSS
82 to 87
MA2 to MA7
88
VDD
89
MA8
90
VSS
91
MA9/MNT0
92
MNT1/MNT1
93
MNT2/MNT2
94
XMOE
95
XCAS
96, 97
MDB8, MDB9
98
VSS
99
MDBA
100
VDD
101, 102
MDBB, MDBC
103
VDD5V
104 to 106
MDBD to MDBF
107
GFS
108
VSS
109
APEO
110
VDD
111
DASYO
112
GNDA5
113, 114
ASF1, AFS2
115
DASYI
116
RFDCC
I/O
I
DVD mode: Serial data request signal input from ZIVA5X-C1F
O
Not used (Pull up)
O
Not used (Pull up)
I
Not used (Pull up)
I/O
Not used (Pull up)
—
Power supply (+5V)
I
Not used (Pull up)
—
Ground (open)
I
Not used
—
Power supply (+3.3V)
I/O
Not used
I/O
Two-way data bus with the D-RAM
—
Ground
I/O
Two-way data bus with the D-RAM
—
Power supply (+5V)
I/O
Two-way data bus with the D-RAM
O
Write enable signal output to the D-RAM
—
Power supply (+3.3V)
O
Row address strobe signal output to the D-RAM
O
Address signal output to the D-RAM
—
Ground
O
Address signal output to the D-RAM
—
Power supply (+3.3V)
O
Address signal output to the D-RAM
—
Ground
O
Address signal output to the D-RAM
O
EEPROM ready signal output to CXP973064
O
Address signal output to the D-RAM
O
Output enable signal output to the D-RAM
O
Column address strobe signal output to the D-RAM
I/O
Two-way data bus with the D-RAM
—
Ground
I/O
Two-way data bus with the D-RAM
—
Power supply (+3.3V)
I/O
Two-way data bus with the D-RAM
—
Power supply (+5V)
I/O
Two-way data bus with the D-RAM
O
Guard frame sync signal output to CXP973064-226R
—
Ground
O
Absolute phase error signal output
—
Power supply (+3.3V)
O
RF binary signal output
—
Ground
—
Filter connected terminal for selection the constant asymmetry compensation
I
Analog signal input after integrated from the RF binary signal
I
Input terminal for adjusting DC cut high-pass filter for RF signal
Description
CX-JTD8
81
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