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Schematic Diagram -Main Section (3/5) - Sony ICD-UX200 Service Manual

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3-7.
PRINTED WIRING BOARD – MAIN Section (3/5) –
1
2
MAIN BOARD (3/5)
A
CS2
MAIN
LCD_A0
D5003
5
BOARD
CPU_VDD_3.1
1SS400TE-61
(1/5)
VCC_3.3
(Page 15)
DGND
B
C
D
DGND
MAIN
FM_CLK
12
BOARD
SDA
(4/5)
SCL
(Page 18)
E
MAIN
VCC_3.3
13
BOARD
AIRQ
(5/5)
VBUS
(Page 19)
F
DPC
KEY_AD0
MAIN
KEY_AD1
3
BOARD
VBUS
(1/5)
DM
(Page 15)
DP
G
CN5001
16P
DGND
16
KEY_AD0
15
KEY_AD1
14
SW
B
A-B REPEAT
13
BOARD
VOL-
12
CN8000
DOWN
11
(Page 21)
DIVIDE
10
CPU_VDD3.1
9
H
VBUS
8
VBUS
7
NC
6
USB
A
DGND
5
LF8001
BOARD
D-
4
CN8001
D+
3
(Page 21)
DGND
2
DGND
1
I
ICD-UX200/UX200F/UX300/UX300F/UX400F
• See page 10 for Waveforms. • See page 22 for IC Block Diagrams.
3
4
5
R5008
C5017
100
R5012
C5002
47u
10k
0.1u
6.3V
IC5000
12
11
10
9
REAL TIME CLOCK
IC B/D
R5034
4700
13 NC
NC
8
0.6
3.1
X5000
14 X1
SCL
7
0.6
3.1
IC5000
32.768kHz
6
15 X2
SDA
IDT1337GNLGI8
5
R5019
16 NC
NC
220k
CSP
(CHIP SIDE PACKAGE)
2
1 2 3 4
R5020
SERIAL DATA SWITCH
100k
R5011
10k
C5003
R5017
0.1u
22k
S5011
S5012
3
1
3
1
A-B
ERASE
4
2
4
2
R5007
2200
C5004
0.1u
S5003
S5005
S5013
3
1
3
1
3
1
4
2
4
2
4
2
DIVID
-
+
VOL
6
7
8
3.1
R5033
4700
3.1
S
3.1
Q5003
3.1
LSK3541FS8T2L
SERIAL CLOCK
S
3.1
SWITCH
3.1
Q5004
LSK3541FS8T2L
Q5004
3.1
Q5000
3.1
DTA144EMFS6T2L
D5000
SML-D12M8WT86SM
KEY WAKEUP SWITCH
0
R5021
C5005
10k
0.1u
Q5001
LSK3541FS8T2L
R5023
LED DRIVE
100k
C5007
R5025
1u
1M
S5014
ON
R5022
1M
C5006
OFF
0.1u
DSP
(SPEED CTRL)
17
17
ICD-UX200/UX200F/UX300/UX300F/UX400F
9
10
11
12
R5024
470k
C5008
1
C5012
C5013
R5009
1M
C5014
C5009
1u
C5015
C5010
C5016
C5011
D5000,5001
(LCD BACK LIGHT)
D5001
SML-D12M8WT86SM
R5028
R5032
R5031
R5027
470
22
22
2200
0.4
D5002
SML-521MUW
0
(OPR)
S
Q5002
LSK3541FS8T2L
1.6(3.1)
LED DRIVE
0
S
R5029
1M
13
14
BACKLIGHT
LCD_RESET
SCL
SDA
CPU_32K
MAIN
8
AIRQ
BOARD
KEY_WAKEUP
(1/5)
LED_R
(Page 15)
LED_G
SDO0
SCK0
CN5000
22P
1
VSS
2
CSB
3
RESET
4
A0
5
SCL
6
SDA
7
VSS
8
VDD
9
VOUT
10 CAP3N
LCD9001
1u
(
)
11 CAP3P
LIQUID
CRYSTAL
12 CAP1N
DISPLAY
1u
13 CAP1P
PANEL
14 CAP2P
1u
15 CAP2N
16 CAP4P
17 V0
1u
18 V1
1u
19 V2
1u
20 V3
1u
21 V4
22 VSS
MAIN
DGND
14
BOARD
CPU_VDD_3.1
(5/5)
UNREG_2.4
(Page 19)

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